The present invention relates generally to switching power converters. More particularly, the present invention relates to providing an open loop half-bridge converter with improved switching frequency control. Even more particularly, the present invention relates to an improved half-bridge converter control method for use in a switch mode power supply.
Power systems that use intermediate bus architecture have in recent years become a desirable solution as opposed to more traditional centralized power supplies or distributed converters in isolation. Intermediate bus architecture generally offers greater power quality at a lower cost due in part to use of highly efficient and power-dense unregulated intermediate bus converters. These converters generate intermediate bus voltages in an acceptable range for delivery to local point-of-load (POL) regulators.
Designers have conventionally resisted variable frequency control schemes for switch-mode converters as fundamentally undesirable with respect to constant-frequency control, having more difficult implementation in addition to potential electromagnetic interference. This is particularly true for steady-state operation, which has conventionally had the primary attention of the designers rather than irregular operations that are associated with startup or short circuit conditions.
As such, various topologies have been designed to implement soft switching and constant-frequency control. Soft switching, or more specifically zero voltage switching in the context of this application, relates to providing a driver signal that turns on each switch in an oscillating inverter when the voltage waveform across the switch drops to zero, thus eliminating or minimizing associated switching losses.
Conventional switch-mode bus converters as known in the art commonly use an open-loop, half-bridge topology operating at full duty cycle. During startup and short circuit conditions a pulse width modulator symmetrically reduces the pulse width to each inverter switch while maintaining a constant switching frequency to reduce energy in the primary switches and the transformer. However, during these conditions the half-bridge converter is operating in what is known in the art as a hard switching mode, where the switches are not turned on in accordance with zero volt switching. Due to the hard switching during startup and short circuit conditions, energy recovery snubber circuits are frequently used to protect the switching components and reduce parasitic ringing that would otherwise occur. The losses which are dissipated in these snubbers may be prohibitive, particularly at high switching frequencies.
In other half-bridge topologies an asymmetrical duty cycle has been used to prevent switching losses. This also does not provide optimal efficiency, as such a system may for example have undesired circulating currents during the off time of the PWM or require larger duty cycle ranges.
These conventional techniques are particularly unsuitable with respect to intermediate bus architecture converters, which require high efficiency and flexibility and are located within a limited physical area.
There is a need for a half-bridge converter that ensures zero-volt switching during all operating conditions to eliminate the use of snubbers and unstable operation that is inherent to hard switching during startup and short circuit conditions.
Further, there is a need for a converter topology that reduces energy in the primary switches and transformer without reducing the pulse width of the driving signals to the inverter.